About
FAQ
Howto
Download
Links
Developers
Project Page
EM8300 register map
Fixed registers
Summary
| Address | Name | Description |
|---|---|---|
| 0x1FB0 | EM8300_AUDIO_RATE | Audio clockgenerator samplerate double/half/normal. Default value 0x62 |
| 0x1F42 | HSYNC_LO | Horizontal Sync lo-byte |
| 0x1F43 | HSYNC_HI | Horizontal Sync hi-byte |
| 0x1F45 | VSYNC_HI | Vertical Sync hi-byte |
| 0x1F47 | ? (Used in em8300_video.c: em8300_video_setup()) | |
| 0x1F4D | EM8300_I2C_PIN | I2C-bus pin state |
| 0x1F4E | EM8300_I2C_OE | I2C-bus pin output enable control |
| 0x1F5E | ? (Used in em8300_video.c: em8300_video_setup()) | |
| 0x1FFA | EM8300_INTERRUPT_ACK | Interrupt acknowledge. Write 0x2 to this register to acknowledge interrupt. |
| 0x1FFB | ? (Used in em8300_video.c: em8300_video_setup()) | |
| 0x2000 | RISC-core reset. |
I2C registers
| Address | Bit range | Bit range description |
|---|---|---|
| 0x1F4D | 0 | ADV7175 video encoder reset |
| 1 | Clockgenerator transfer shift-register state to output | |
| 2 | I2C-bus 2 SCL | |
| 3 | I2C-bus 1,2 SDA and clockgenerator shift-register data | |
| 4 | I2C-bus 1 SCL | |
| 5 | Clockgenerator shift-register clock | |
| 6-7 | Unused | |
| 8-15 | These bits selects the pins which are to be updated. Example setting SDA is done by writing 0x808 to the register. At read accesses the logic level of the pins are read from bits 8-15 | |
| 0x1F4E | 0-15 | This register controls the state of the output control. Same bit configuration as register 0x1F4E. |
Microcode dependent registers
| Name | Description | Value | Value description |
|---|---|---|---|
| MV_Command | Mpeg Video Command | 0x0 | Stop |
| 0x1 | Pause | ||
| 0x3 | Play and strictly obey PTS | ||
| 0x4 | Play Intra Frames Only | ||
| 0x6 | Play and leave syncing to the em8300 (do not strictly obey PTS). Smoother playback, but stream has to be synced first. Read more here. | ||
| 0x10 | Unknown. Used during setup. (Flush Buffer?) | ||
| 0x11 | Unknown. Used during setup. (Flush Buffer?) | ||
| MV_Status | |||
| MV_BuffStart_Lo | |||
| MV_BuffStart_Hi | |||
| MV_BuffSize_Lo | |||
| MV_BuffSize_Hi | |||
| MV_RdPtr_Lo | The lower 16 bits of the pointer to the address at which the em8300 is currently reading video data from. | ||
| MV_RdPtr_Hi | The higher 16 bits of the read pointer. | ||
| MV_Threshold | Lowest fill level accepted by the decoder before issuing a "FIFO needs to be refilled" interrupt. | ||
| MV_Wrptr_Lo | The lower 16 bits of the address to which you should write video data. | ||
| MV_Wrptr_Hi | The higher 16 bits of the write pointer. | ||
| MV_PCIRdPtr | Pointer to the next FIFO slot to be read by the decoder. If MV_PCIRdPtr = MV_PCIWrPtr the FIFO is empty. | ||
| MV_PCIWrPtr | Pointer to the next available free FIFO slot | ||
| MV_PCISize | Number of registers occupied by the FIFO slot headers | ||
| MV_PCIStart | Here starts the FIFO slot headers. Each FIFO slot header item occupies 4 register. This gives a total of MV_PCISize / 4 slots. See Video FIFO section for a description of the slot header data structure | ||
| MV_PTSRdPtr | Video timestamp fifo read pointer. | ||
| MV_PTSSize | |||
| MV_PTSFifo | |||
| MV_SCRSpeed | Playback speed | 0x9 | Normal speed for microcode version < 0x29 |
| 0x900 | Normal speed for microcode version >= 0x29 | ||
| MV_SCRlo | This is the lower 16 bits of the internal clockgenerator running at 45000Hz. This is used for pts syncing. | ||
| MV_SCRhi | This is the higher 16 bits of the internal clockgenerator. | ||
| MV_FrameCntLo | |||
| MV_FrameCntHi | |||
| MV_FrameEventLo | |||
| MV_FrameEventHi | |||
| MV_AccSpeed | |||
| Width_Buf3 | |||
| MA_Command | Audio Command | 0x0 | Stop |
| 0x1 | Pause | ||
| 0x2 | Play | ||
| MA_Status | |||
| MA_BuffStart_Lo | |||
| MA_BuffStart_Hi | |||
| MA_BuffSize | |||
| MA_BuffSize_Hi | |||
| MA_Rdptr | |||
| MA_Rdptr_Hi | |||
| MA_Threshold | |||
| MA_Wrptr | |||
| MA_Wrptr_Hi | |||
| Q_IrqMask | |||
| Q_IrqStatus | IRQ status. This is read by the ISR in order to determine what caused the interrupt | 0x80XX | Interrupt was requested by the EM8300 chip |
| 0x2 | Video FIFO needs refilling | ||
| 0x8 | Audio FIFO needs refilling | ||
| 0x10 | Vertical blanking | ||
| Q_IntCnt | |||
| MA_PCIRdPtr | |||
| MA_PCIWrPtr | |||
| MA_PCISize | |||
| MA_PCIStart | |||
| SP_Command | Sub Picture command | 0x0 | |
| Sub Picture command | 0x2 | ||
| SP_Command | 0x102 | ||
| SP_Status | |||
| SP_BuffStart_Lo | |||
| SP_BuffStart_Hi | |||
| SP_BuffSize_Lo | |||
| SP_BuffSize_Hi | |||
| SP_RdPtr_Lo | |||
| SP_RdPtr_Hi | |||
| SP_Wrptr_Lo | |||
| SP_Wrptr_Hi | |||
| SP_PCIRdPtr | |||
| SP_PCIWrPtr | |||
| SP_PCISize | |||
| SP_PCIStart | |||
| SP_PTSRdPtr | |||
| SP_PTSSize | |||
| SP_PTSFifo | |||
| DICOM_DisplayBuffer | |||
| Vsync_DBuf | |||
| DICOM_TvOut | TV-out settings | bit 15 | Pause output |
| bit 14 | General output on | ||
| 0x10 | 16:9 aspect ratio | ||
| 0x1 | Interlace control ? | ||
| DICOM_UpdateFlag | |||
| DICOM_VSyncLo1 | |||
| DICOM_VSyncLo2 | |||
| DICOM_VSyncDelay1 | |||
| DICOM_VSyncDelay2 | |||
| DICOM_Display_Data | |||
| PicPTSLo | |||
| PicPTSHi | |||
| Error_Code | |||
| DisplayHorSize | |||
| Line21Buf1_Cnt | |||
| Line21Buf2_Cnt | |||
| TimeCodeHi | |||
| TimeCodeLo | |||
| AUTH_Challenge | |||
| AUTH_Response | |||
| AUTH_Command | |||
| Timer_Cnt | |||
| Ovl_Addr | |||
| Button_Color | |||
| Button_Contrast | |||
| Button_Top | |||
| Button_Bottom | |||
| Button_Left | |||
| Button_Right | |||
| SP_Palette | |||
| DICOM_FrameTop | |||
| DICOM_FrameBottom | |||
| DICOM_FrameLeft | |||
| DICOM_FrameRight | |||
| DICOM_VisibleTop | |||
| DICOM_VisibleBottom | |||
| DICOM_VisibleLeft | |||
| DICOM_VisibleRight | |||
| DICOM_BCSLuma | |||
| DICOM_BCSChroma | |||
| DICOM_Control | 0x9afe | ||
| 0x9efe | |||
| DICOM_Controlx | |||
| MV_CryptKey | |||
| DICOM_Kmin | |||
| MicroCodeVersion | |||
| ForcedLeftParity | |||
| L21_Buf1 | |||
| L21_Buf2 | |||
| Mute_Pattern |
FIFOs
Video FIFO slot data structure
| Offset | Description |
|---|---|
| 0 | Flags |
| 1 | Upper 16 bits of physical address to data block |
| 2 | Lower 16 bits of physical address to data block |
| 3 | Datablock size |
Audio FIFO slot data structure
| Offset | Description |
|---|---|
| 0 | Upper 16 bits of physical address to data block |
| 1 | Lower 16 bits of physical address to data block |
| 2 | Datablock size |
Subpicture FIFO slot data structure
| Offset | Description |
|---|---|
| 0 | Flags |
| 1 | Upper 16 bits of physical address to data block |
| 2 | Lower 16 bits of physical address to data block |
| 3 | Datablock size |
